Explain like I'm five · Systems

What is a CPU Pipeline?

CPU pipelining, told as a story about setting up several repair benches and overlapping several cars' repairs at once.

one mechanic alone does intake, check, repair, finishthe cars behind just wait the whole time

One mechanic handles a car from start to finish alone.The cars behind just wait the whole time.

the next one starts only after this one finishestaking turns is fair, but the total time stretches outwhat if several benches worked at once?

Handling one car at a time makes finishing all the cars take much longer.What if several benches worked at once?

intakecheckrepairpaintfinisha pipeline overlaps several cars across several benches at onceat any instant, four cars are each at a different stage

A pipeline overlaps several cars across several benches at once.At any instant, four cars are each at a different stage.

Fetchbrings in the next instruction (job)
Decodereads what the work is
Executeactually does the repair
Writebackwrites down the result of the work
same instant, different stagescar 1 — now at 'paint'car 2 — now at 'repair'car 3 — now at 'check'car 4 — now at 'intake'more cars finish per hour than when fixing one at a time

At the same moment, each car is at a different stage.More cars finish per hour than when fixing one at a time.

normally the benches never sit idlea missing part can stall every car behind it (a pipeline stall)overlapping finishes more cars — but one jammed bench stalls the benches behind it

Sometimes a car still has to wait on the one ahead.Overlapping finishes more cars, but one jammed bench stalls the benches behind it.

In one breath

A CPU pipeline splits instruction processing into stages and runs them overlapped, like several benches at once, to raise overall throughput.

CPU pipelining splits processing a single instruction into stages — fetch, decode, execute, memory access, writeback — and overlaps them so different hardware handles each stage simultaneously. Because the next instruction can start before the previous one finishes, throughput rises significantly. However, data hazards (waiting on an earlier result) and control hazards (flushing the pipeline after a mispredicted branch) can cause stalls.

When grown-ups say it

Pipelining
Overlapping several cars across several benches. Significantly raises how much gets done in a given time (throughput).
Fetch
The stage that brings in the next instruction. The first stage of the pipeline.
Decode
The stage that reads what the instruction means. Unpacks the instruction into an executable form.
Execute
The stage that actually does the work. Where the computation actually happens.
Data Hazard
Needing to wait on the result of the car ahead. Happens because an earlier instruction's result isn't ready yet.
Branch Prediction
Guessing ahead which path comes next. A wrong guess means flushing the pipeline.
Pipeline Stall
Cars behind stalling because a part hasn't arrived. Occurs when a hazard arises.
Throughput
How many cars get processed in a given time. The core goal of pipelining.
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